The invention is directed to a basic cell for a gate array arrangement in CMOS technology, in which first transistors of one conductivity type lie behind one another in a first region, and an identical number of second transistors of the other conductivity type lie behind one another in a second region arranged adjacent to said first region, with the electrodes of the transistors in the first region and the electrodes of the transistors in the second region respectively proceeding in one direction.
Gate array arrangements are known (for example, Hitachi Review, Vol. 33 (1984) No. 5, pages 261 through 266, European Patent No. 011 9059-A2). In such gate array arrangements, cell regions, or cells in a defined arrangement are provided on a chip. An example of such a gate array arrangement is shown in FIG. 1 and in FIG. 2 of European Patent No. 011 9059-A2. The basic cells are composed of n-channel and p-channel transistors which are arranged in the cell regions in a defined way. By connecting the n-channel and p-channel transistors per basic cell, the basic cell can be specified for the realization of a basic function, and it can be used, for example, to perform a logic function or a memory function. As described in the Hitachi Review, a basic cell can, for example, be composed of ten transistors that are connected to one another such as to produce a RAM memory cell having one input or two inputs. A logic function, for example, a NAND function can be realized by other connections of the transistors.
European Patent No. 011 9059-A2 yields basic cells composed of four transistors, respectively two p-channel and two n-channel transistors, and illustrates how logic functions can be realized by interconnecting the basic cells.
The individual basic cells in the gate array arrangement must be connected to one another for setting functions. This occurs via wiring channels which are either arranged between the rows of basic cells or proceed over the rows of basic cells.
The realization of memories having different capacities was hitherto achieved in various ways. Bistable circuits were used for storage structures having low capacity. These bistable circuits are composed of a plurality of gates and therefore require a relatively great number of basic cells of a gate array for storing an information unit. Memories having high capacity were realized by a memory block having a defined capacity and designed as a universal cell integrated into the core region of a chip. In this arrangement, the capacity of a memory can only be selected in steps of the memory capacity of this universal cell, also referred to as macrocell, and a plurality of different gate array masters had to be produced to provide memory areas of various size. Finally, the space requirement for such memories was relatively great since wiring channels had to be arranged between the rows of basic cells.